1. Field of the Invention
This invention relates to a CMOS intermediate potential generation circuit formed in a semiconductor integrated circuit (IC). The inventive circuit generates a low power intermediate potential from a power source voltage supplied to the device.
2. Background of the Invention
The invention uses various materials which are electrically either conductive, insulating or semiconducting, although the completed semiconductor circuit device itself is usually referred to as a "semiconductor". The invention refers to a method of controlling addressed devices, and is not restricted to implementations which involve memory devices or semiconductor devices.
In an integrated circuit (IC) device, it is often useful to have a potential that is at some intermediate value between the supply potentials to the IC. Many different kinds of circuits have been developed to generate intermediate potentials.
FIG. 1 shows perhaps the simplest way to generate an intermediate potential. Two resistors R1 and R2 are connected in series from a potential supply V.sub.cc to a lower supply potential V.sub.ss. The voltage available between the two resistors is the intermediate potential. This circuit, known as a resistive voltage divider, has a disadvantage of consuming excessive amounts of supply current.
FIG. 2 shows another kind of intermediate potential generation circuit, developed by Okada, et al., U.S. Pat. No. 4,663,584, hereby incorporated by reference. A notable feature of this circuit is that transistors Q3 and Q4 drive intermediate potential V.sub.02 only when V02 strays from a predetermined value. The chain from VCC to V.sub.22 formed by R3, Q1, Q2 and R4 require minimal standby current. In this manner, an intermediate potential with a much higher drive is obtained, while consuming only enough supply current to generate a reference voltage and to adjust V.sub.02 when it strays from the desired potential.
FIG. 3 shows a similar circuit, determined by reverse engineering a device made by Hitachi, Ltd., of Tokyo, Japan, which has Okada's minimal standby current advantage along with the added advantage of quicker response time in V03 to VCC transitions. The circuit of FIG. 3 accomplished this speed improvement by replacing resistors R3 and R4 of FIG. 2 with transistors Q5 and Q6 gated by node VX3 as shown in FIG. 3. For example, if V.sub.cc undergoes a positive transition, the difference between VX3 and the rising V.sub.cc causes Q5 to turn on harder than normal. Node V1 is pulled up which turns on transistor Q3, which in turn pulls up node V03. When VX3 stabilizes to V.sub.cc /2, Q3 turns off and V03 stabilizes to the new V.sub.cc /2. Similarly, node V03 is pulled down by Q4 when V.sub.cc undergoes a negative transition.
An intermediate potential generation circuit is desired that can provide faster response to load variations and supply voltage transitions, higher current drive, and lower standby current than the circuits of FIGS. 2 and 3.